1. Field of the Invention
The present invention relates to a plasma display panel module, and more specifically, a plasma display panel module with a sustainer board.
2. Description of the Background Art
Recently, a plasma display panel (hereinafter, referred to as “PDP”) with easiness of producing a larger size panel has received attention as a plate display device. A PDP usually displays images by adjusting a gas discharge period of each pixel by digital video data. A typical example of the PDP is an alternating current PDP with three electrodes that is driven by alternating current, as is shown in FIG. 1.
FIG. 1 is an enlarged view of a discharge cell that comprises an alternating current PDP known in the prior art.
A discharge cell 30 illustrated in FIG. 1 has an upper plate that includes an upper substrate 10, sustain electrodes 12A and 12B that are formed on the upper substrate 10 in order, an upper dielectric layer 14, and a protective film 16, and an lower plate that includes a lower substrate 18, a data electrode 20 that is formed on the lower substrate 18 in order, a lower dielectric layer 22, a division wall 24, and a phosphor layer 26.
The sustain electrodes 12A and 12B includes a scan electrode 12A and a sustain electrode 12B. Each of the sustain electrodes 12A and 12B is comprised of a transparent electrode and a metal electrode that decrease high resistance by the transparent electrode.
The scan electrode 12A provides a scan signal for an address discharge and a sustain signal for a sustain discharge, and the sustain electrode 12B provides a sustain signal. The data electrode 20 is formed so that the electrode intersects with the sustain electrodes 12A and 12B. The data electrode 20 provides a data signal for the address discharge.
Electrical charges that is generated by a discharge are accumulated in the upper dielectric layer 14 and the lower dielectric layer 22. The protective film 16 prevents the upper dielectric layer 14 from damaging by sputtering in the discharge, and increases the discharge efficiency of secondary electrons. It is possible to decrease the discharge voltage externally applied by the upper dielectric layer 14, the lower dielectric layer 22, and the protective film 16.
The division wall 24 forms a discharge space with the upper substrate 10 and the lower substrate 18. The division wall 24 is formed in parallel to the data electrode 20, and prevents ultraviolet rays generated by the gas discharge from leaking into adjacent cells.
The surface of the lower dielectric layer 22 and the division wall 24 is covered by the phosphor layer 26, and the phosphor layer 26 generates red, green, or blue visible ray. Inert gases for the gas discharge, such as helium (He), neon (Ne), argon (Ar), xenon (Xe), or Kripton (Kr), mixed discharge gases by those inert gases, or excimer gases that can generate ultraviolet rays by the discharge, are charged in the discharge space.
The discharge cell 30 with this structure maintains the discharge by generating the surface discharge between the sustain electrodes 12A and 12B, after it is selected in the opposite discharge between the data electrode 20 and the scan electrode 12A. Due to this, in the discharge cell 30, the phosphor layer 26 emits light because of ultraviolet rays generated in the sustain discharge, and thereafter visible rays are released.
The gradation display of a PDP is comprised of a process of adjusting the sustain discharge period in the discharge cell 30 by video data, that is, adjusting the number of the sustain discharge. Then, color of a pixel is displayed by combination of three discharge cells that red, green, and blue phosphor layers 26 are applied.
FIG. 2 is a diagram illustrating the whole alignment of electrodes in a PDP and includes the discharge cell 30 illustrated in FIG. 1. In FIG. 2, the discharge cell 30 locates in each of the intersections of scan electrode lines Y1 through Ym, sustain electrode lines Z1 through Zm, and data electrode lines X1 through Xn.
The scan electrode lines Y1 through Ym provide a scan pulse and a sustain pulse so that the discharge cell 30 is scanned by the line, and maintain the discharge in the discharge cell 30. The sustain electrode lines Z1 through Zm provide a common sustain pulse, and maintain the discharge in the discharge cell 30 with the scan electrode lines Y1 through Ym. Data electrode lines X1 through Xn provide a data pulse synchronized with the scan pulse by the line, so that the discharge cell 30 that the discharge is maintained by the theoretical value of the data pulse is selected.
A typical example of this PDP driving method is an address and display separation (hereinafter, referred to as “ADS”) driving method. In the method, the address period and the display period (in other words, the sustain period) are separated.
In the ADS driving method, one frame is divided into sub-fields corresponding to video data, and each of the sub-fields is redivided into the reset period, the address period, and the sustain period. Each of the sub-fields includes the same reset period RPD and the same address period APD, and also includes the sustain period SPD that different weighted values are assigned. Due to this, the PDP display gradation corresponding to the video data is displayed by the combination of sustain periods that maintain the discharge with the video data.
FIG. 3 is a common driving waveform that is provided for the PDP illustrated in FIG. 2 in a sub-field 1 SF of some sub-fields.
The PDP equalizes all of the wall charges in the discharge cell 30 by erasing a certain amount of the wall charges, after it generates the full lighting discharge that uses a reset pulse RP in the reset period RPD as shown in FIG. 3.
Because of this, the reset pulse RP is provided with the scan electrode lines Y1 through Ym. The reset pulse RP is composed of a ramp-up pulse and a ramp-down pulse. The ramp-up pulse gradually increases to the peak voltage Vr on the basis of the step voltage Vs, and the ramp-down pulse gradually decrease to the base voltage 0V.
The ramp-up pulse generates the first dark discharge in all the discharge cells 30. Then, the ramp-down pulse and a bias pulse BP that is provided with the sustain electrodes Zi through Zm generates the second dark discharge in all the discharge cells 30.
The ramp-down pulse decreases wall discharges generated in the scan electrode lines Y1 through Ym and the sustain electrode lines Z1 through Zm to a certain amount, and this equally initializes wall charges in all of the discharge cells 30. In the reset period RPD, the voltage of data electrode lines X1 through Xn is fixed at the base voltage 0V.
In the address period APD, the scan pulse SP is provided with the scan electrode lines Y1 though Ym by the line, and the data pulse DP is selectively provided with each of the data electrode lines X1 through Xn in synchronization with the scan pulse SP.
Due to this, the address discharge is generated in the discharge cells that the scan pulse SP and the data pulse DP are provided, and this generates sufficient amount of wall charges for the next sustain discharge. On the other hand, the address discharge is not generated in the discharge cells that the scan pulse SP and the data pulse DP are not provided, and this maintains the off-state.
In the sustain period SPD, a sustain pulse SUSPy and a sustain pulse SUSPz are alternately provided with the scan electrode lines Y1 through Ym and the sustain electrode lines Z1 through Zm, and the state of discharge cells that is decided in the address period APD is maintained.
In the concrete, the discharge cells, which sufficient amount of wall discharges is formed in the address period APD, maintain the on-state of the discharge by the sustain pulse SUSPy and the sustain pulse SUSPz, and the discharge cells in the off-state maintain the off-state without any discharge.
In the erase period EPD that follows the sustain period SPD, an erase pulse EP is provided for the sustain electrode lines Zi through Zm and the erase discharge is generated, and this erases wall discharges in all of the discharge cells 30.
To provide the driving waveform with the PDP shown in FIG. 2, a driving device is installed on the back of a heat sink 64, which is located on the backside of a PDP 40 as is shown in FIGS. 4 and 5.
The driving device shown in FIGS. 4 and 5 has a driving board Y 45, a sustainer board Z 48, a data driver board 50, a control board 42, and a power board that is not shown in the diagrams.
The driving board Y 45 drives the scan electrode lines Y1 through Ym in the PDP 40, and the sustainer board Z 48 drives the sustain electrode lines Z1 through Zm. The data driver board 50 drives the data electrode liens X1 through Xm, and the control board 42 controls the driving board Y 45, the sustainer board Z 48, and the data driver board 50. The power board that is not shown in the diagrams supplies power with the control board 42, the driving board Y 45, the sustainer board Z 48, and the data driver board 50.
The driving board Y 45 includes a scan driver board 44 and a sustainer board Y 46. The scan driver board 44 generates the reset pulse RP and the scan pulse SP, which are shown in FIG. 3 of PDP 40. The sustainer board Y 46 generates the sustain pulse Y SUSPy.
The scan driver board 44 provides the scan pulse SP with the scan electrode lines Y1 through Ym in the PDP 40 via a flexible printed circuit (hereinafter, referred to as “FPC”) 51. The sustainer board Y 46 provides the sustain pulse Y SUSPy with the scan electrode lines Y1 through Ym via the scan driver board 44 and a FPC Y 51.
The sustainer board Z 48 generates the bias pulse BP and the sustain pulse Z SUSz, which are shown in FIG. 3, and provides them with the sustain electrode lines Z1 through Zm in the PDP 40 via a FPC Z 52.
The data driver board 50 generates the data pulse DP shown in FIG. 3, and provides this to the data electrode lines X1 through Xn in the PDP 40 via a FPC X 54.
The control board 42 generates each of the timing control signals X, Y, and Z. The control board 42 provides a timing control signal Y with the driving board Y 45 via a first FPC 56, provides a timing control signal Z with the sustainer board Z 48 via a second FPC 58, and provides a timing control signal Z with the data driver board 50 via a third FPC 60.
In case of driving a PDP module with this structure, a electric current path in the sustain period SPD is as follows. Firstly, when sustain pulse Y SUSPy is provided with the scan electrode lines Y1 through Ym from the driving board Y 45, the first electric current path follows the direction of: the driving board Y 45, the scan electrode lines Y1 through Ym, a panel capacitor, the sustain electrode lines Z1 through Zm, the sustainer board Z 48, the heat sink 64, and the driving board Y 45.
Also, when the sustain pulse Z SUSPz is provided with the sustain electrode lines Z1 through Zm from the sustainer board Z 48, the second electric current path follows the direction of: the sustainer board Z 48, the sustain electrode lines Z1 through Zm, the panel capacitor, the scan electrode lines Y1 through Ym, the driving board Y 45, the heat sink 64, and the sustainer board Z 48.